Recently, a thin film transistor (TFT) formed on the surface of an insulating substrate, such as glass or the like, has been widely used as a switching device in a matrix configuration to control a liquid crystal display device. The liquid crystal display device is used widely in televisions and computer monitors. In a liquid crystal display device, two glass plates are joined with a layer of a liquid crystal material sandwiched thereinbetween. The glass plates have conductive films coated on their surfaces where at least one of the substrates is transparent. The substrates are connected to a power source to change the orientation of the liquid crystal material so that various areas of the liquid crystal display cell can be accessed by proper patterning of the conductive film. The thin film transistors are used to separately address areas of the liquid crystal cells at very fast rates. As the requirements for the resolution of liquid crystal monitors increase, it becomes desirable to separately address a plurality of areas of the liquid crystal cell, called pixels. In a modern display panel, more than 1,000,000 pixels are normally present. The same number of thin film transistors must be formed on the glass plates so that each pixel can be separately addressed and latched into one of two stable states.
One of the major types of thin film transistor devices used today is a back channel etched (BCE) thin film transistor. A BCE type thin film transistor is fabricated by first forming a gate conductor on an upper surface of an insulating substrate, a gate dielectric layer of silicon nitride or silicon oxide is then deposited over the gate conductor. A substantially hydrogenated intrinsic amorphous silicon is then deposited over a hydrogen plasma treated silicon nitride layer. A layer of N+ doped amorphous silicon is subsequently deposited over the amorphous silicon layer. Thereafter, a layer of source/drain metalization is deposited over the N+ doped silicon layer and subsequently patterned to form respective source and drain electrodes. Plasma enhanced chemical vapor deposition (PECVD) process is commonly used for depositing materials in the fabrication of TFTs.
In a fabrication process for TFTs, numerous dielectric material layers are deposited. The dielectric materials employed include silicon nitride, silicon oxide, and any other suitable dielectric materials. The dielectric materials are used to insulate in, for example, a gate dielectric layer or a passivation layer. When electrical contacts must be made through a dielectric layer, the layer is etched by first applying a photomask to the layer to pattern openings for the contacts. The contact openings are then etched by a suitable etchant gas and filled in a subsequent metal deposition process. In a conventional-TFT fabrication process, a step coverage problem is frequently encountered in the etching and the subsequent metal deposition processes.
For example, a silicon nitride layer are conventionally etched using SF.sub.6 /O.sub.2 chemistry as shown in FIGS. 1A through 1C. The etch rate of a silicon nitride film using SF.sub.6 /O.sub.2 gas at 20 m-torr and 50 m-torr are shown in FIG. 1A. It is seen that at a chamber pressure of 20 m-torr, an etch rate of approximately 200 nm/min is obtained. At a higher chamber pressure of 50 m-torr, an etch rate of approximately 300 nm/min is obtained. An enlarged cross-sectional view of a semiconductor device 10 etched at 20 m-torr is shown in FIG. 1B. A vertical sidewall in the silicon nitride opening is obtained by the SF.sub.6 /O.sub.2 gas etching. An enlarged cross-sectional view of an attached semiconductor device 20 using the same etchant gas at 50 m-torr is shown in FIG. 1C. A vertical sidewall 22 in the silicon nitride layer is obtained showing a small undercut 24.
The etching of silicon nitride using SF.sub.6 /O.sub.2 presents a profile control problem which leads to poor step coverage in the subsequent metal deposition process. The step coverage problem occurs when sharp corners in the opening created by the vertical sidewalls are not covered by the subsequently deposited metal. As a result, voids at the corners are formed. The voids increase the resistance of the metal conductor and decrease the efficiency of the device. Therefore, the formation of vertical sidewalls in nitride openings should be avoided.
It is therefore an object of the present invention to provide a method of etching a dielectric layer in a semiconductor device that overcomes the drawbacks and shortcomings associated with the prior art.
It is another object of the present invention to provide a method for etching a dielectric layer in a semiconductor device that improves profile control.
It is a further object of the present invention to provide a method of etching holes or trenches in a dielectric layer of a semiconductor device and then filling the holes or trenches without step coverage.
It is yet another object of the present invention to provide a method of etching openings of holes or trenches in a dielectric layer of a semiconductor device without forming vertical sidewalls in the etched openings.
It is still another object of the present invention to provide a method of etching openings in a dielectric layer of a semiconductor device using an etchant gas mixture of SF.sub.6 /Cl.sub.2.
It is further object of the present invention to provide a method of etching openings in a dielectric layer of a semiconductor device producing sloped sidewalls in the openings.
It is a further object of the present invention to provide a method of etching openings in a dielectric layer of a semiconductor device producing sloped sidewalls having a taper between about 20.degree. and about 85.degree. in the openings.
It is a further object of the present invention to provide a method of etching openings in a dielectric layer of a semiconductor device producing sloped sidewalls in the openings such that void formations in a subsequent deposition process are avoided.